In nonvolatile semiconductor memory devices, especially NAND-type flash memory devices, because the memory cells have a high aspect ratio, and the gate lengths continue to shrink, a pattern breakdown or misalignment may occur when a gate is formed. In one approach to solve these problems, an NAND-type flash memory device with a flat cell structure, in which a stack of a thin polysilicon film layer (hereinafter referred to as FG poly electrode) and a trap film layer comprised of SiN or HfO are used as a floating gate electrode and a high dielectric film is used as an IPD (Inter Poly Dielectric) film is employed. In the configuration of this flat cell structure, a capacitance of the high dielectric film can be high while maintaining a low aspect ratio, and thus the design has a good write/erasure characteristic.
Here, since the film thickness of the FG poly electrode is reduced, a structure for reliably interconnecting the control gate of a transistor and the FG poly electrode, and a method of reliably manufacturing the structure are needed.